AI/ML Physical Design Engineer for Sub-2nm PPA

Samsung Semiconductor in San Jose is seeking a Senior Physical Design AI/ML Engineer for the Logic Pathfinding Lab. You will apply AI/ML to improve design simulation accuracy and throughput, and contribute to DTCO knob optimization for sub-2nm nodes.

This role requires deep experience in cell architecture, PDK generation, and logic integration. You will collaborate across teams including TD Korea, writing design rules, and guiding multiple organizations.