Clocks ASIC Engineer – Shape GPU/CPU Timing, Equity

NVIDIA is seeking an ASIC clocking engineer to shape the clock domain for GPUs and CPUs in Santa Clara. You will work with front-end, floorplanning and back-end teams to optimize PPA and deliver robust clocking solutions in RTL.

The role requires strong Verilog RTL skills, Python scripting, and a good understanding of clock networks and silicon issues. This hybrid position offers equity and comprehensive benefits with competitive base pay.