IT & Software

CPU Architecture and RTL Design

AMD

Cambridge · England · United Kingdom

Overview

As a CPU Core MicroArchitect/RTL Design Engineer at AMD, you will help shape the next generation of high-performance cores, focusing on the core pipeline and cache subsystem. You’ll collaborate closely with hardware and software teams to define architecture, verify designs, and drive power efficiency and timing convergence, from RTL to post-silicon support. You’ll work at the cutting edge of CPU technology within a collaborative, results-driven environment. This role offers the opportunity to influence AMD’s ambitious CPU roadmap and contribute to technology that moves the world forward.

Responsibilities

  • RTL design and coding for processor core pipeline with a focus on caches and memory subsystem
  • Collaborate with hardware and software teams to define high-level architecture
  • Contribute to microarchitecture definition of next-generation high-performance cores
  • Contribute to design verification, synthesis, power reduction, timing convergence, and floorplanning
  • Post-silicon support to ensure successful bring-up

Key requirements
  • Industry experience in silicon design in the CPU domain
  • RTL development with CPU-oriented tools
  • Experience with high-performance CPU design and microarchitecture
  • Knowledge of processor architecture and logic design
  • RTL coding for high-speed processor
  • Power-saving techniques
  • Exposure to physical design and verification methods
  • Awareness of synthesis, place-and-route, and timing closure concepts
  • Experience from clean-sheet design to product tape-out and post-silicon debug
  • Proven microarchitecture development experience (patents, publications, or product features)
  • Strong problem-solving and debugging skills
  • Strong communication and collaboration skills
  • Relentless problem-solving with critical thinking and creativity
  • RTL coding for high-speed processor
  • Processor architecture and logic design
  • High-performance CPU design and microarchitecture
  • Power-saving techniques

Reference: WJ-799_28572214

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