DFT Engineer

In this role you will drive robust Design-for-Test for next-generation ASICs, supporting high-quality silicon from design to volume production. You will work within an ASIC team to shape DFT strategy across chips, subsystems and IP, collaborating with design, verification, physical implementation and product engineering. The role offers exposure to advanced test infrastructures and end-to-end silicon bring-up, with a meaningful impact on product quality and time-to-market. You will solve complex DFT challenges and help scale test solutions for production.

• Define DFT strategies at chip, subsystem and IP level
• Implement structural and functional DFT methodologies across complex ASIC designs
• Insert and integrate scan, MBIST, EDT, SSN and IJTAG-based test infrastructure
• Verify DFT implementation and debug related issues throughout the design cycle
• Support implementation and sign-off, including timing constraints, timing closure, power analysis and formal equivalence checking
• Work closely with Physical Design and Verification teams to ensure successful integration
• Support ATPG generation, silicon bring-up and manufacturing test
• Mentor and support other engineers within the team

• Experience working within modern ASIC or SoC development flows
• Strong experience with Siemens Tessent DFT tools
• Good understanding of complex DFT challenges, including clocking, reset architecture and IP integration
• Experience with: ATPG, MBIST, Scan architecture, DFT verification and simulation debug, UPF and low-power verification concepts
• Good Tcl scripting skills (Python is also beneficial)
• Collaborative approach with excellent troubleshooting and debugging skills

• collaborative
• troubleshooting
• mentoring or coaching
• Siemens Tessent DDT tools
• ATPG
• MBIST