End-to-End Verification Engineer - SystemVerilog

Riverlane is seeking a Verification Engineer in Cambridge to own end-to-end verification and drive the quality of our hardware and embedded software stacks. You will design scalable testbenches using SystemVerilog, implement checkers, and develop reference models to ensure robust, reliable systems.

Collaboration with designers will be essential to define plans and improve coverage. You will work across block- and system-level designs, maintain the verification environment, and track regressions