Hardware Engineer

We’re designing novel general-purpose computer architecture that scales to thousands of cores. We’re using the properties of interaction nets, namely locality of operations, inherent parallelism, and linearity to fix some of the biggest bottlenecks of CPU design. No cache coherency, no reorder buffers, no memory ordering model. Read the background.

Hardware Engineer

Responsibilities

You’ll be working together with us on the design and implementation of the architecture and have the ability to meaningfully shape all components of the chip. This work can include:

• RTL implementation
• RTL verification
• FPGA prototyping
• Architectural design and experimentation in our chip simulator.

Required qualifications

• Extensive experience in RTL design with Verilog
• Knowledge of architecture design
• Willingness to learn the complex properties of interaction nets that make the chip possible
• Experience with FPGA prototyping
• Software development experience (e.g. Python and Rust)
• Familiarity with hardware simulation tools

Location

Preferred Cambridge, UK. We sponsor Visa if required and help with relocation.

Compensation

£150k / $200k in addition to significant equity.