Hybrid PCIe Verification Engineer (UVM/SystemVerilog)

AMD is seeking a Verification Engineer to join the PCIe Subsystem team. You will develop and refine SystemVerilog/UVM testbenches, work with architects and RTL designers, and drive verification plans for new PCIe features.

The role demands strong communication and problem-solving to ensure robust RTL designs. Ideal candidates have hands-on experience with PCIe, SATA, Ethernet, and a track record in complex verification environments, with a focus on memory sub-systems and performance goals.