Mixed-Signal IP Integration Engineer: High-Speed ASICs

Ciena Corporation in Ottawa is seeking a hardware-focused ASIC design engineer to design mixed-signal macros within an ASIC flow for high-baud-rate optical modems.

You will generate Verilog, SPICE netlists, and provide IP integration support, using Cadence and Synopsys tools. This role emphasizes analog/digital timing handoff and test methodologies.

The team collaborates across analog and digital disciplines, applying rigorous design and verification practices.