New Grad: Mixed-Signal IP Integration Engineer

Ciena Corporation in Ottawa, Ontario, is seeking a Mixed-Signal IP Integration Engineer - New Grad to join our team and contribute to the design and integration of mixed-signal macros within an ASIC flow for next-generation high-baud-rate optical modems.

The role involves working with Verilog/RTL, SPICE, and Cadence tools, aiding analog-digital timing handoff and static timing analysis, and collaborating across design teams. Prior internship or co-op in IC design is valued.