Principal ASIC Design Engineer: RTL & Microarchitecture Lead

Yoh, a Day & Zimmermann company, is seeking a Principal ASIC Design Engineer to own front-end design for complex, high-performance networking silicon used in AI infrastructure.

The role demands hands-on RTL development, multiple tapeouts, and close collaboration with architecture, verification, emulation, DFT, and physical design teams to translate product requirements into robust microarchitecture and production-ready RTL.