Principal Engineer, Design Verification

In this role, you will lead verification activities for mixed-signal ICs within the CSS domain at ADI. You’ll work across multiple business units to shape verification strategies, develop advanced testbenches, and drive issue resolution from concept to release. You will collaborate with analog co-sim and firmware teams, mentoring junior engineers and supporting post-silicon verification. This is a hands-on opportunity to influence verification standards in a fast-growing area at a global leader.

• Verify complex designs and subsystems using leading-edge methods
• Contribute to verification strategies and methodologies
• Develop testbench architectures using UVM or formal methods
• Define verification plans, coverage, and tests for block/chip levels
• Collaborate with design to generate closure metrics and plans
• Debug GLS and timing violations with designer input
• Mentor junior engineers on SoC verification
• Lead verification efforts at IP/SoC level including planning and reporting
• Support post-silicon verification with cross-functional teams

• Bachelor or Master in Engineering (Electronic Engineering) or equivalent
• Experience building and leading small verification teams
• Strong English communication and customer-facing experience as verification lead
• Proven track record in IP and SoC level verification
• Expertise in verification plans, coverage analysis, constrained random, assertion-based and formal verification with SystemVerilog
• Proficiency in UVM for unit and SoC level testbench development and integration
• Strong debugging and analytical skills
• Proficiency in scripting (Makefile, Python, TCL/tsh, Perl)
• 10-15 years in ASIC design verification

• strong interpersonal and teamwork abilities
• excellent communication
• self-motivated and enthusiastic
• SystemVerilog
• UVM
• formal verification techniques