IT & Software

Principal GPU HW Verification Engineer

Imagination Technologies Group

Bristol · Bristol · United Kingdom

Overview

In this role you will lead verification for a GPU component within Imagination’s PowerVR Graphics group, shaping verification strategy and sign-off. You’ll develop verification plans, build UVM testbenches, and drive closure through metrics and reviews. You will mentor teammates and influence design discussions to improve verification outcomes. The position offers the chance to impact cutting-edge graphics IP and help scale verification methodologies for complex RTL designs.

Responsibilities
  • Oversee verification activities for a GPU component or subsystem from planning to sign-off
  • Develop verification plans and build/maintain UVM testbench components
  • Monitor, track, and report verification metrics for closure
  • Provide verification-focused feedback during design spec discussions
  • Implement UVM testbenches including tests, sequences, coverage, assertions, and plans
  • Own task definition, effort estimation, and progress tracking
  • Contribute to enhancement and evolution of GPU verification methodologies
  • Lead, mentor, and support team members in verification activities
  • Engage in design and verification reviews, suggesting improvements
Key requirements
  • Demonstrated experience in developing verification environments for complex RTL designs
  • Strong understanding of constrained-random verification methodologies and challenges of verification closure
  • Ability to define verification requirements and design testbenches
  • Expertise in root-cause analysis of complex issues
  • Deep knowledge of SystemVerilog and UVM
  • Capability to develop and enhance verification flows
  • Familiarity with ASIC design methodologies, flows, and tools
  • Proficiency in planning, estimating, and tracking personal tasks
  • Experience managing multiple projects simultaneously
  • Strong communication skills (verbal and written)
  • excellent communication
  • collaboration
  • problem solving
  • SystemVerilog
  • UVM
  • constrained-random verification

Reference: WJ-747_30134461

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