Senior ASIC RTL Front-End Engineer — SoC Innovation

Capgemini Engineering seeks an Expert Front-End ASIC RTL Designer to join a team working on advanced semiconductor technologies. You will design, develop and debug ASIC IPs, collaborating across design, verification and software teams to deliver high-quality SoCs.

The role involves RTL design in Verilog/SystemVerilog/VHDL, IP integration at the SoC level, and adherence to DFT, CDC, RDC, Lint, and UPF guidelines in a dynamic engineering environment.