Senior Design Verification Engineer - UVM & SystemVerilog

KTek Resourcing is seeking design verification engineers with UVM experience to join our ASIC DV team in Canada. You will lead or contribute to verification of 4–5 ASIC design blocks, develop UVM-based environments, and ensure coverage closure in collaboration with customers in the EST timezone.

The role requires strong SystemVerilog/UVM expertise and the ability to own verification deliverables end-to-end across assigned blocks, with the customer retaining testbench ownership.