Senior DFT Engineer

In this DFT Engineer role, you will shape chip-level and block-level DFT strategies for complex ASICs. You’ll implement scan architectures, compression, boundary scan, and MBIST/LBIST to achieve high test coverage and smooth silicon bring-up. You’ll collaborate with RTL, verification, physical design, and test teams, supporting flows with DFT constraints and performing verification. You’ll lead bring-up, debugging, and failure analysis, and develop automation to boost DFT productivity. This position offers impact on product reliability within Cirrus Logic’s collaborative, inclusive culture.

• Define and implement chip-level and block-level DFT strategies for complex ASICs
• Develop and integrate scan architecture, compression logic, boundary scan, MBIST, and LBIST solutions
• Drive ATPG generation, fault simulation, diagnosis, and coverage closure
• Collaborate with RTL, verification, physical design, and test engineering teams
• Support synthesis, STA, and physical design flows with DFT-based constraints
• Perform DFT verification using simulation
• Lead silicon bring-up, debug and failure diagnosis activities
• Develop automation scripts and methodologies to improve DFT productivity and quality

• Bachelor in Electrical Engineering or related discipline with proven DFT experience
• Strong understanding of digital design and test methodologies
• Hands-on experience with scan insertion and scan compression
• ATPG and fault simulation
• MBIST/LBIST implementation
• JTAG / IEEE 1149.1 standards
• Test coverage analysis and diagnosis
• Experience with Siemens Tessent and Synopsys TetraMAX / TestMAX
• Scripting skills in Tcl & Python
• Familiarity with Verilog/SystemVerilog and simulation environments
• Excellent debugging and problem-solving skills
• Good communication and collaboration skills

• communication
• collaboration
• problem-solving
• Scan insertion
• Scan compression
• ATPG