Senior Engineer

In this role you verify Arm’s SoC Management IP, crafting verification environments and plans for IP blocks. You collaborate across architecture, design, and verification to ensure high-quality IP for a range of Arm-based systems. You apply SystemVerilog/UVM methodologies to expose and resolve RTL issues, drive coverage, and advance verification infrastructure. The role offers impact by improving reliability of core IP used in real-time to cloud-scale platforms. You’ll be at the heart of delivering robust, scalable verification in a cross-functional team.

• hybrid working
• accommodation support during recruitment
• equal opportunity employer

• Develop and own verification plans for IP blocks based on architecture and build specifications
• Build and implement SystemVerilog/UVM-based verification environments, including testbenches, stimulus, and checkers
• Define functional and code coverage goals and drive coverage closure
• Debug RTL and verification issues, working with build and architecture teams to resolve problems
• Complete regression testing and analyze failures to root cause
• Support the advancement and refinement of verification methodologies and infrastructure
• Participate in building and verification reviews, providing feedback to improve build quality and verifiability
• Collaborate with teams across Arm to ensure delivery of high-quality IP

• Experience in RTL verification, including development of constrained-random environments
• Strong proficiency in SystemVerilog and familiarity with UVM or similar methodologies
• Experience in writing test plans, developing testbenches, and driving coverage closure
• Good debugging and problem-solving skills in complex simulation environments
• Understanding of verification fundamentals, including functional coverage and assertions
• Experience with scripting languages (e.g., Python, Perl, or similar) for automation
• Strong communication skills and ability to work effectively within a team

• strong communication skills
• team collaboration
• problem-solving
• SystemVerilog
• UVM or similar methodologies
• constrained-random verification