Senior FPGA Architect: Ultra-Low Latency Systems

Platform Recruitment is seeking a Senior FPGA Engineer in Cambridge to oversee RTL design on ultra-low-latency platforms. You will architect RTL on high-end FPGAs, drive verification environments, and collaborate with firmware, software and infrastructure teams to optimise full-stack performance.

Required 7+ years FPGA/RTL experience, SystemVerilog, and hands-on with Vivado or Quartus. Familiarity with AXI/PCIe/Ethernet interfaces is preferred.