Senior FPGA Engineer — Ultra-Low Latency Systems Lead

Platform Recruitment in Cambridge is seeking a Senior FPGA Engineer to join a global team developing ultra-low latency technology. You will oversee FPGA system design from architecture to verification, enabling the next generation of infrastructure.

The role requires deep hands-on RTL design experience, SystemVerilog expertise, and proficiency with Vivado or Quartus. You will collaborate across firmware, software, and infrastructure teams to optimise performance and mentor other engineers.