Senior High-Speed Analog Architect for AI Interconnects

Celero Communications, Inc. is seeking a Principal High-Speed Analog Circuit Design Engineer to lead the design of high-speed analog blocks for next-generation transceivers and AI interconnect tech. You will architect circuits, supervise layouts, and drive verification across advanced process nodes from concept to silicon. The role requires a Masters or PhD in EE with 5+ years in analog design, strong tool proficiency (Virtuoso, Spectre, ADE) and experience in CMOS design flows.

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