Senior I/O Chiplet Verification Engineer (SystemVerilog/UVM)

BTADesignServices in Ottawa, Canada, is seeking a Senior I/O Chiplet Verification Engineer to lead verification of high-speed chiplet interfaces and die-to-die interconnects. You will design verification plans, develop SystemVerilog/UVM environments, and collaborate with architecture, RTL, firmware, and IP partners to achieve sign-off with thorough coverage across protocols and reset/latency requirements.

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