Senior PCIe/CXL Verification Engineer (Subsystem)

Arm is seeking an experienced verification engineer to verify PCIe and CXL subsystems at the sub-system level. You will craft test plans, develop SystemVerilog/Verilog/UVM testbenches and debug failures, while partnering with RTL designers and architects across the UK, US, Canada and India to drive next‑generation SoCs on leading nodes.

The role offers hybrid working and opportunities to influence verification strategies and methodologies.