Senior STA Physical Design Engineer - PnR & Signoff Expert

Astera Labs is seeking a Senior Principal STA Physical Design Engineer to drive RTL-to-GDS sign-off for its connectivity ASICs used by major cloud providers and OEMs. On-site in San Jose, you will collaborate with RTL, verification, and frontend teams to ensure robust, scalable sign-off across complex designs.

You’ll bring deep PnR, timing, and EM-IR experience, with strong scripting skills and a track record of handling high-speed transceiver timing challenges in advanced nodes.