Senior Staff Verification Engineer (f/m/div)

In this role, you will lead the development and optimization of IP verification environments within the R&D team. You’ll own complex IP verification using SystemVerilog-UVM test benches and drive robust test strategies. You’ll create coverage models, write constrained tests, and ensure sign-off targets including functional safety. You’ll troubleshoot issues and influence verification direction for future projects. This is a chance to shape high-assurance semiconductor solutions for a greener, digital world.

• Hybrid workplace
• Diversity & Inclusion
• Equal opportunities
• global collaboration
• opportunity to impact green and secure IoT solutions

• Drive development and optimization of IP verification environments
• Own complex IP verification using SystemVerilog-UVM test benches
• Create functional coverage models and constrained random tests
• Ensure test benches meet sign-off targets (coverage and safety)
• Debug failing test cases and collaborate in Design/Concept meetings
• Shape verification strategy and enhance test bench architecture for future projects

• Bachelor’s degree in Electrical/Electronic Engineering or related field
• 8+ years in Verification Engineering with SystemVerilog-UVM experience
• Strong understanding of verification concepts and SystemVerilog design/testbench fundamentals
• Eagerness to learn and apply UVM methodologies
• Understanding of debugging workflows and test issue analysis tools
• Strong problem-solving, teamwork, and time-management skills
• Fluency in English

• collaboration
• problem-solving
• time management
• SystemVerilog
• UVM
• verification concepts