Senior Verification Engineer

In this role you verify complex digital and mixed-signal ASICs to ensure functional correctness and robustness. You will develop verification plans, build UVM-based testbenches, and drive regression and coverage for both block and full-chip levels. You collaborate with design teams to translate specs into verification requirements and mentor junior engineers to improve methodologies. This opportunity places you at a leading semiconductor hub in Edinburgh, offering impactful work in a high-growth environment.

• Competitive base salary
• RSUs
• annual bonus

• Develop and execute verification plans for complex mixed-signal ASICs
• Create and maintain UVM-based SystemVerilog testbenches
• Write and run test cases to verify functionality, performance, and corner cases
• Perform block-level and full-chip verification with simulation, coverage analysis, and regression management
• Collaborate with design engineers to define verification requirements
• Analyze and resolve issues from verification and post-silicon validation
• Mentor junior engineers and drive verification methodology improvements
• Participate in code reviews and advance design and verification best practices

• 5+ years experience in digital and/or mixed-signal design verification
• Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
• Solid understanding of digital design principles, RTL design, and ASIC development flows
• Experience with scripting languages (Python, Perl, Shell, etc.)
• Familiarity with formal verification, assertion-based verification, and coverage-driven verification techniques
• Excellent problem-solving skills and attention to detail

• collaboration
• mentoring
• problem-solving
• SystemVerilog
• UVM
• Synopsys VCS