Senior Verification Engineer

In this role you verify complete mixed-signal IC developments, shaping verification strategies and test infrastructure. You will lead a verification team, develop reusable testbenches, and contribute to methodology improvements. You’ll work on cutting-edge projects within a global organisation and collaborate across groups to ensure high-quality ICs. This is a hands-on position with opportunities to influence verification practices and project outcomes.

• personal and professional development
• flat culture
• hybrid remote work schedule
• in-office collaboration as needed

• Define IC verification plans from requirements to test cases
• Lead teams of verification engineers to deliver verified ICs
• Create reliable and reusable testbenches for subsystems and ICs
• Contribute to verification specialist groups and methodology discussions
• Coach and support the verification team to follow and improve methodologies
• Hands-on involvement in project design and verification

• Degree in Electronics/Computer Science or related discipline (BEng/BSc/MEng/MSc)
• Metric-driven verification experience including requirements extraction and coverage analysis
• SystemVerilog and SystemVerilog Assertions (SVA)
• Testbench design with UVM/OVM/VMM frameworks
• RTL and testbench debugging; OOP; gate-level (including SDF)
• Scripting skills (Ruby, sh/csh, TCL, Make, Perl)
• Power-aware verification using CPF/UPF

• leadership and team management
• collaboration and cross-functional communication
• mentoring and coaching
• SystemVerilog
• SVA
• UVM/OVM/VMM