Senior Verification Engineer

In this role you validate RTL implementations for Arm-based SoCs, ensuring new features and existing functionality meet architecture and quality standards. You collaborate with RTL designers and architects to understand specs, build and enhance verification environments, and drive coverage closure. You will shape verification plans, mentor teammates, and contribute to evolving verification practices. This position sits at the intersection of hardware and software elements, offering impact through robust IP verification in a globally distributed team.

• hybrid working options
• accommodations during recruitment
• diverse and inclusive environment

• Collaborate with RTL designers and architects to understand specifications and microarchitecture details
• Develop and enhance validation setups, including stimulus generation, checking, and coverage infrastructure
• Create and execute verification plans and test plans
• Implement verification strategies with other engineers
• Drive functional and code coverage closure
• Debug and resolve complex design and verification issues
• Contribute to continuous improvement of verification methodologies and infrastructure
• Provide technical mentorship and support to less experienced engineers

• 5+ years in IP, subsystem, or SoC verification
• Strong proficiency in SystemVerilog and Verilog
• Experience with UVM or other industry-standard verification methodologies
• Experience developing constrained-random verification environments and reusable components
• Experience developing verification strategies and test protocols
• Understanding of SoC verification including software integration
• Experience with Python, Perl, or similar scripting languages
• Strong debugging, analytical, and problem-solving skills
• Strong interpersonal and communication skills for cross-site collaboration

• 跨地域团队协作能力
• 沟通能力强
• 分析与问题解决能力
• SystemVerilog
• Verilog
• UVM