Senior Verification Engineer

In this role you will lead UVM-based verification for digital IP and modem subsystems, collaborating with RTL, architecture, and wider engineering teams through FPGA deployment to ASIC tape-out. You will design verification plans, build SystemVerilog/UVM environments, and drive coverage and regression efforts to ensure functional and performance targets. The position emphasizes cross-functional collaboration and continuous improvement of verification processes, including AI-assisted productivity enhancements. This is a high-impact role shaping next-generation wireless and satellite communications at the forefront of technology.

• Develop verification plans from architecture and design specs
• Create and maintain SystemVerilog/UVM verification environments
• Develop testbenches, assertions, scoreboards and coverage models
• Run directed and constrained-random verification
• Drive coverage analysis and closure
• Debug RTL and verification issues
• Support IP, subsystem and system-level integration
• Contribute to regression, automation and CI workflows
• Participate in design reviews and verification sign-off
• Mentor junior engineers
• Apply AI-assisted approaches to improve verification productivity while maintaining quality

• 3+ years of experience verifying digital ASIC and/or FPGA designs
• Strong SystemVerilog and UVM experience
• Good understanding of RTL design and digital hardware principles
• Experience with coverage-driven and assertion-based verification
• Strong debugging and problem-solving skills
• Linux experience alongside scripting in Python, Tcl and/or Bash
• Experience working across RTL, architecture and verification teams
• Degree in Electronic Engineering, Computer Engineering or a related discipline

• mentoring
• collaboration
• problem-solving
• SystemVerilog
• UVM
• verification environments