Senior Verification Engineer

In this role you will lead UVM-based verification for complex wireless IP and modem subsystems, ensuring functional, performance, and quality targets ahead of FPGA deployment and ASIC tape-out. You will work within a specialist RTL team, collaborating across engineering groups to verify, debug, and sign off on designs. The position offers mentoring responsibility for junior engineers and exposure to challenging, hardware-centric verification projects. This role appeals to you if you enjoy shaping verification strategies and applying automation to deliver robust subsystems at scale.

• Develop verification plans from design and architecture specs
• Create and maintain SystemVerilog/UVM environments
• Develop testbenches, assertions, scoreboards and coverage models
• Carry out directed and constrained-random verification
• Analyse coverage and debug RTL and verification issues
• Support subsystem and system-level integration
• Contribute to automation, regression testing and CI workflows
• Participate in design reviews and verification sign-off
• Mentor and support junior engineers

• Degree in Electronic Engineering, Computer Engineering, or a related discipline
• At least 3 years' experience verifying digital ASIC and/or FPGA designs
• Strong SystemVerilog and UVM experience
• Good understanding of RTL design principles and hardware implementation
• Experience with coverage-driven and assertion-based verification
• Linux proficiency with Python, Tcl or Bash scripting skills
• Strong analytical, debugging and problem-solving skills
• Experience using AI to accelerate verification while maintaining quality
• Ability to collaborate effectively across multiple engineering teams

• collaboration across teams
• mentoring
• analytical thinking
• SystemVerilog
• UVM
• RTL design principles