Senior Verification Engineer, ASIC/FPGA & SystemVerilog

YOH SOLUTIONS LTD is seeking a Senior Verification Engineer to join its engineering team in Cambridge, UK. You will verify complex RTL designs in a collaborative ASIC/FPGA environment, ensuring functional and performance targets are met before production hardware.

You will lead verification planning, develop SystemVerilog/UVM testbenches, and mentor junior engineers while coordinating with design and systems teams across project lifecycles.