Senior Verification Engineer - Chiplet Focus
European Recruitment BV
Elevate your career as a Senior Verification Engineer focusing on chiplet projects in Ottawa with a leading ASIC services provider. Collaborate on advanced I/O technologies to effectively validate multi-protocol high-speed interconnections.
This role involves establishing and executing verification plans for complex silicon solutions. You will partner with architecture, design, and firmware teams, translating detailed specifications into actionable verification goals. Your contributions will span high-speed datapaths, firmware management, and the full verification lifecycle, ensuring quality outcomes prior to tape-out and product launch.
Key Responsibilities: • Develop thorough verification plans mapping requirements to test scenarios • Design reusable SystemVerilog/UVM environments for efficient testing • Integrate vendor VIP and models for end-to-end connectivity verification • Verify static-switch mappings and high-speed protocol behaviours • Collaborate with firmware teams to validate boot sequences and configurations
Requirements: • 10+ years of ASIC verification experience with tape-out ownership • Expertise in SystemVerilog and UVM for testbench architecture • Proven development of verification plans and debugging skills • Experience with high-speed interfaces and complex SoCs • Strong skills in scripting and automation management
Utilize your expertise in high-speed I/O and verification to drive success at a dynamic ASIC services provider. #J-18808-Ljbffr
This role involves establishing and executing verification plans for complex silicon solutions. You will partner with architecture, design, and firmware teams, translating detailed specifications into actionable verification goals. Your contributions will span high-speed datapaths, firmware management, and the full verification lifecycle, ensuring quality outcomes prior to tape-out and product launch.
Key Responsibilities: • Develop thorough verification plans mapping requirements to test scenarios • Design reusable SystemVerilog/UVM environments for efficient testing • Integrate vendor VIP and models for end-to-end connectivity verification • Verify static-switch mappings and high-speed protocol behaviours • Collaborate with firmware teams to validate boot sequences and configurations
Requirements: • 10+ years of ASIC verification experience with tape-out ownership • Expertise in SystemVerilog and UVM for testbench architecture • Proven development of verification plans and debugging skills • Experience with high-speed interfaces and complex SoCs • Strong skills in scripting and automation management
Utilize your expertise in high-speed I/O and verification to drive success at a dynamic ASIC services provider. #J-18808-Ljbffr
Reference: WJ-3875_12923926