Senior Verification Engineer (IP verification)

In this role you verify and validate complex IPs (Crypto Accelerators, HW DVFS components, PCIe controllers, interconnect fabrics) to ensure interoperability with software and across subsystems. You will define test plans, build tests in C, and develop SystemVerilog/Verilog testbenches while debugging failures. Collaborate with architecture, design, silicon validation, FPGA/board teams and planning leads to advance verification methodologies. You’ll explore AI-based verification approaches to scale quality and coverage. This is a chance to shape world‑class IP for a broad set of market segments within a collaborative, growth‑driven culture.

• hybrid working
• accommodation support during recruitment
• visa sponsorship for employer (where applicable)

• Write test plans and define test methodologies
• Develop C-based software tests and SystemVerilog/Verilog testbenches/tests
• Debug test failures and issues
• Plan with project management on tasks, schedules, and progress reporting
• Collaborate with architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA/board teams

• Verilog/SystemVerilog HDL expertise
• Experience with UVM, formal, or power-aware verification
• SoC verification using Embedded low-level programming including C/C++ tests and assembly (ARM preferred)
• Experience across verification lifecycle (requirements, test plans, testbench implementation, test case development)
• Strong problem solving and debugging skills
• Knowledge of IP/SoC verification flow and strategy
• ARM-based builds and/or ARM System Architectures
• Clock domain crossing verification
• Experience with GLS, DFT/DFD
• UPF Power Aware verification
• Automation scripting (Tcl, Perl, Python)
• Willingness to apply AI-based methods to verification

• Problem solving
• Collaborative mindset
• Cross-functional communication
• Verilog/SystemVerilog HDL
• UVM/formal/power-aware verification
• C/C++ low-level testing