Senior Verification Engineer - Media IP

As a Verification Engineer in Arm's Systems Media IP team, you will own verification for DPU subsystems and complex units, shaping verification architectures and driving quality gates. You collaborate with architecture, design, and software teams to ensure seamless DPU integration into complete systems. You will build scalable UVM environments, define verification plans, and push for automation and regression efficiency. This role offers impact across automotive, IoT, and client markets, contributing to high-performance IP that enables customers to build innovative products. You will lead cross-team fixes and influence technical decisions with data-driven insights.

• hybrid working
• accommodations on request
• visa sponsorship support for employer costs
• equal opportunity employer

• Own verification for a DPU subsystem or complex unit from planning to sign-off
• Contribute to verification architecture, planning, integration strategy and quality criteria
• Architect reusable SystemVerilog/UVM environments and verification IP
• Define verification plans, coverage models and sign-off criteria
• Identify risks early and drive mitigation across teams
• Review architecture/design changes for correctness and observability
• Lead resolution of complex unit-, cross-unit-, or system-level failures
• Align verification activities across unit, subsystem, and DPU teams
• Drive improvements in methodology, automation, reuse, and regression efficiency
• Use verification data to identify quality gaps and guide priorities
• Build links with architecture, design, software, and Arm teams for successful integration

• Strong SystemVerilog and UVM expertise with complex verification environments
• Hands-on verification with on-chip bus protocols (AMBA APB, AXI) or similar
• Experience creating verification plans from scratch for complex IP/subsystems
• Experience owning verification of multi-unit subsystems or complex units
• Experience developing verification testbenches
• Programming experience in Python, C, or equivalent
• Familiarity with verification workflows (regression, version control, linting)
• Knowledge of verification tooling and infrastructure
• strong debugging and problem-solving abilities
• excellent cross-team communication

• clarity under ambiguity
• stakeholder alignment
• ownership mindset
• SystemVerilog
• UVM
• AMBA APB