Senior Verification Engineer, Media IP & DPU
CamWebDir
Arm is seeking an experienced verification engineer to lead the verification of a DPU subsystem within the Systems Media IP team. You will architect high-performance SystemVerilog/UVM environments and ensure robust verification across multiple units, aligning with project plans and schedules.
You will work with Python/C for tooling and contribute to verification strategies, tests, coverage, and integration into complete systems.
#J-18808-LjbffrReference: WJ-766_22385041