Senior Verification Engineer - SV/UVM & Formal

TekWissen Group is seeking a Verification Engineer V in Markham, Ontario, to join the Display IP team. You will define, develop, and execute verification solutions for complex IP and SoC designs, partnering with architects, RTL designers, firmware, software, and validation teams to ensure first-pass silicon success.

The ideal candidate has 8-10+ years of ASIC/SoC verification experience and strong SystemVerilog/UVM skills, with a track record of developing verification plans, coverage models,