STA Engineer

In this role you will contribute to the full chip development lifecycle, from early design to silicon delivery and product release. You will work in a collaborative team to optimize performance, power and area across ASIC/SoC designs. You will tackle timing, setup/hold, clock gating, and signal integrity challenges, driving timing closure across implementation stages. You will develop and enforce timing constraints and models, collaborating with Physical Design, RTL Design and Verification teams. This opportunity offers meaningful impact within a close-knit hardware-focused culture, enabling you to shape how complex semiconductor products reach silicon bring-up and production.

• Perform full-chip and block-level static timing analysis on ASIC/SoC designs
• Drive timing closure across implementation stages from synthesis to sign-off
• Analyze and resolve setup, hold, clock gating and signal integrity issues
• Develop timing constraints and ensure accurate timing models and methodologies
• Collaborate with Physical Design, RTL Design and Verification to optimise PPA
• Support sign-off activities including STA, timing verification and silicon bring-up readiness
• Debug and resolve complex timing issues in advanced process nodes
• Contribute to an integrated, cross-functional hardware development lifecycle

• Strong academic background in Electronics, Electrical Engineering or related discipline
• Proven experience in Static Timing Analysis, Physical Design or ASIC implementation
• Deep understanding of timing closure methodologies and sign-off flows for advanced ASIC/SoC designs
• Strong knowledge of Synopsys PrimeTime, Design Compiler and place-and-route tools
• Experience on complex, high-performance semiconductor products, ideally in AI, HPC or data centre domains
• Strong scripting skills in Tcl, Perl or Python to automate timing analysis
• Excellent communication and ability to work in cross-functional teams

• communication
• collaboration
• problem-solving
• Synopsys PrimeTime
• Design Compiler
• place-and-route tools