Staff Verification Engineer

In this role you own IP verification for cutting-edge automotive designs and collaborate with a team delivering IP for Automotive Microcontrollers. You define verification plans, map requirements, and develop SV-UVM test benches to tackle complex issues. You debug failures, build functional coverage models, and participate in reviews to meet quality and safety targets. You proactively improve verification efficiency and help shape the overall verification strategy and architecture.

• Define verification plan and requirements mapping
• Develop SV-UVM test bench and solve complex problems
• Debug failing test cases and root cause analysis
• Define and write a functional coverage model
• Participate in reviews to ensure test bench quality, coverage, and sign-off
• Proactively increase verification efficiency and mitigate risks
• Contribute to verification strategy and architecture of IP test benches

• At least 5 years in verification with IP-level focus mandatory
• Expertise in SystemVerilog and UVM
• Experience with EDA tools for design and simulation
• Scripting skills in Python or Perl
• Knowledge of ISO26262 and ASIL-D functional safety requirements

• Collaborative teamwork
• Strong problem-solving mindset
• Proactive risk management
• System Verilog
• UVM
• IP-level verification