Staff Verification Engineer

In this role you will own verification across block, subsystem, and multi-FPGA designs within a stealth-like hardware team in Cambridge. You will shape the verification strategy, build scalable environments, and help drive progress in quantum hardware systems. You’ll work closely with cross-functional hardware peers to address complex challenges and have a meaningful impact on emerging technology. This is a chance to apply deep verification expertise in a cutting-edge, collaborative setting with broad visibility across the hardware stack.

• bonus
• benefits
• visa sponsorship for UK-based engineers
• hybrid work arrangement

• Lead verification strategy and execution across block, subsystem, and multi-FPGA designs
• Develop scalable, high-performance UVM environments for complex architectures
• Drive verification with focus on coverage, risk reduction, and system-level behavior
• Collaborate with Lead Verification Engineer and cross-functional hardware teams
• Debug challenging issues spanning RTL, simulation, and hardware platforms

• Strong hands-on expertise in SystemVerilog and UVM
• Proven debugging skills across RTL, simulation, and hardware
• Experience owning verification planning and strategy in commercial environments
• Comfortable in fast-moving environments with evolving requirements
• Exposure to C, C++, or Python
• Formal verification experience would be a plus

• Curiosity
• Drive to solve problems
• Collaborative mindset
• SystemVerilog
• UVM
• RTL